Designers are constantly striving to improve programmable data processors such as microprocessors and digital signal processors. Often desired improvements involve making the programmable data processor capable of executing additional data processing functions. Such additional data processing functions can be achieved by proposing a new programmable data processor with a new instruction set architecture defining processor operations. However, it is considered desirable to code such new instructions within the same instruction word length of a prior programmable data processor. This permits users, customers of the original data processor vendor, to re-use their prior investment in programming tools and system designer expertise in using the new functions. Such an upgrade of an existing instruction set architecture merely requires an incremental change by the customer. An entirely new data processor with a new instruction set architecture would require a radical change by the customer.
A known manner to address this problem is to change an instruction decoder to detect the desired additional functions and to control operation of a functional unit to achieve the function. One problem with this approach is the limitation of opcode space. Opcode space is the theoretical space defined by the bits of an instruction word available for instruction definition. Not all bits of an instruction word are available for instruction definition. It is conventional to use some instruction bits to define two data registers for source operands and a further instruction bits to define a destination instruction registers. It is common for programmable data processors to have 32 such data registers. Thus 3×log2 32 or 15 instruction word bits are needed just to specify data registers. Other instruction word bits are commonly used for additional signaling and control functions. With many programmable data processors employing 32-bit instruction words, bits that can be devoted to opcodes are limited. In many known data processors few unallocated opcodes exist.
Another problem faced by designers of programmable data processors is known as code bloat. With instruction lengths generally set at 32 bits, the amount of memory required to store instructions may be very large. It is known that many commonly used instructions could be coded with fewer bits, such as 16 bits because these instructions do not need to specify three data registers or because all possible signaling and control functions are not relevant and need not be coded. In many useful product applications at least a significant portion of the system program could be specified with instruction words shorter than the standard length. The designer is left with the problem of distinguishing between this shorter instruction word code and the normal length instruction word code.
A known solution to these two problems involves data processor modes. The data processor has a normal mode which operates in the same manner as the prior data processor in the same family. An alternative mode enables access to alternate or extended instructions by redefining how the limited opcodes are decoded. These alternate or extended instructions could include smaller length instructions or instructions not present in the original instruction set. Generally such data processor modes are invoked by a mode instruction in each mode. A normal mode instruction when executed switches the data processor to the alternative mode. An alternative mode instruction when executed switches the data processor to the normal mode.
Such data processor modes achieve their purpose of enabling the extended or alternative instructions but introduce additional problems. Tracking the current data processor mode and insuring that the instructions to be executed are appropriate for the current mode is a problem. Often there is a significant overhead in changing modes. This prevents free mixing of normal mode and extended mode instructions. In the case of normal length alternative or extended instructions mode changes can be reduced by providing commonly used instructions in both modes. This may reduce the number of required mode changes but takes up limited opcode space in both modes. When implementing a smaller length instruction set, only commonly used instructions are encoded because of limited opcode space. Thus data processor modes are not a completely satisfactory solution to this problem.